Publications

Authored Works

2026

  1. Under ReviewIMC-CLINIC: Coupled Loss-Informed Newton Iterations for Clipping in Analog In-Memory Computing
    Yung-Chin Chen, Chia-Yu Chen, and Naveen Verma
    Under review at ICLR 2027
    URL
  2. In Prep.Hessian-Guided Mixed ADC Precision for Analog In-Memory Computing Systems on LLM Inference
    Yung-Chin Chen, Ourania Stouraiti, and Naveen Verma
    To be submitted to MLSys 2027
  3. EMNLP FindingsMassive Spikes in LLMs are Bias Vectors: Mechanistic Uncovering and Spike-Free Quantization
    Yung-Chin Chen, Chung Peng Lee, Ze-Wei Liou, and Naveen Verma
    In Findings of the Conference on Empirical Methods in Natural Language Processing (EMNLP), 2026
    URL
  4. TCAS-IIN2N-BP²CIM: A 28nm End-to-End Bit-Parallel, Bit-Parallel Computing-In-Memory DNN Processor with High-bandwidth 14T-SRAM Bitcell
    Tsung-Yen Wu*, Yi-Shuan Pan*, Yung-Chin Chen*, Wei-Chun Tseng*, Jeng-Fu Lin, Han-Chung Liang, Hsin-Che Yang, Chun-Yen Yao, Bing-Chen Wu, Yu-Kai Chen, Jyun-Jhe Chou, Xin-You Liu, Jhen-Yu Wei, Wei-You Dai, Chih-Wei Chen, Sheng-Po Huang, Perng-Fei Yuh, Yih Wang, Chi-Sheng Shih, and Tsung-Te Liu
    IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), 2026
    (* denotes co-1st author)

2025

  1. TVLSIASiM: Modeling and Analyzing Inference Accuracy of SRAM-Based Analog CiM Circuits
    Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, and Kentaro Yoshioka
    In IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2025
    URL
  2. ESSERCA 4541 TOPS/W Saliency-Aware Analog Computing In-Memory Macro with Charge-Domain Saliency Detector
    Shimpei Ando, Satomi Miyagi, Wenlun Zhang, Yung-Chin Chen, and Kentaro Yoshioka
    In IEEE European Solid-State Electronics Research Conference (ESSERC), 2025
    URL

2024

  1. ASP-DACOSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration
    Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, and Kentaro Yoshioka
    In Asia and South Pacific Design Automation Conference (ASP-DAC), 2024
    URL
  2. ICCADPACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation
    Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Shinya Takamaeda-Yamazaki, and Kentaro Yoshioka
    In International Conference on Computer-Aided Design (ICCAD), 2024
    URL
  3. arXivHALO-CAT: A Hidden Network Processor with Activation-Localized CIM Architecture and Layer-Penetrative Tiling
    Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, and Kentaro Yoshioka
    In arXiv, 2024
    URL
  4. SSDMA Saliency-Aware Analog Computing-In-Memory Macro with SAR-Embedded Saliency Detection Technique
    Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Wenlun Zhang, and Kentaro Yoshioka
    In International Conference on Solid State Devices and Materials (SSDM), 2024
    URL
  5. SSDM(Invited) Towards Efficient and Precise Analog Compute-in-Memory Circuits
    Kentaro Yoshioka, Shimpei Ando, Satomi Miyagi, Yung-Chin Chen, and Wenlun Zhang
    In International Conference on Solid State Devices and Materials (SSDM), 2024
    URL
  6. JJAPA Review of SRAM-based Compute-in-Memory Circuits
    Kentaro Yoshioka, Shimpei Ando, Satomi Miyagi, Yung-Chin Chen, and Wenlun Zhang
    In Japanese Journal of Applied Physics (JJAP), 2024
    URL
  7. JJAPA Saliency-Aware Analog Computing In-Memory with SAR-Embedded Detection Achieving 18.5% Power Reduction
    Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Wenlun Zhang, and Kentaro Yoshioka
    In Japanese Journal of Applied Physics (JJAP), 2024
    URL

Mentioned Works

  1. JSSCA 818–4094 TOPS/W Capacitor-Reconfigured Analog CIM for Unified Acceleration of CNNs and Transformers
    Kentaro Yoshioka
    IEEE Journal of Solid-State Circuits (JSSC), 2025
    URL
  2. ISSCCA 818–4094 TOPS/W Capacitor-Reconfigured CIM Macro for Unified Acceleration of CNNs and Transformers
    Kentaro Yoshioka
    In IEEE International Solid-State Circuits Conference (ISSCC), 2024
    URL